1. Field of the Invention
This invention relates generally to a process for the fabrication of semiconductor devices and, more particularly, to the process for the electrical interconnection of a plurality of wiring layers in an integrated circuit device.
2. Description of the Related Art
In the related art, contact and via conductive paths are fabricated in integrated circuit devices for providing interconnections between various circuit components and the wiring layers coupling the circuit components. Contact conductive paths connect a first wiring layer with the surface of the semiconductor substrate and/or to the circuit elements fabricated on the surface of the semiconductor substrate. Via conductive paths connect a second wiring layer through a second insulator layer to the first wiring layer. When it is necessary to connect the second wiring layer to the semiconductor substrate, both a via and a contact are used. A conductive path is thus established from the second wiring layer through a via to a conductive region associated with the first wiring layer. From the conductive region associated with the first wiring layer, a contact through the first insulating layer is coupled to the surface of the substrate.
Referring to FIG. 1, an integrated circuit device with a plurality of wiring layers, fabricated according to the related art, is shown. A component 11 is fabricated on the surface of a semiconductor substrate 10. Contacts 13 provide conducting paths through the first insulating layer 12 to selected portions of the first wiring layer 14. The via conductive paths 16 provide a electrical connections from selected portions of the first wiring layer 14 through a second insulating layer 15 and are coupled to predetermined portions of the second wiring layer 17. A final insulating layer 18 is added to protect the second wiring layer 17. The steps for fabricating this portion of an integrated circuit device with a plurality of wiring layers includes the steps of
Forming a first insulating layer over a semiconductor substrate; PA1 Patterning contact holes in the first insulating layer; PA1 Etching the contact holes in the first insulating layer; PA1 Forming the contact hole plugs (i.e., filling the holes with a conductive material); PA1 Forming a first conductive layer over first insulating layer and the plugged holes; PA1 Patterning the first conductive layer; PA1 Etching the first conductive layer to form the first wiring layer; PA1 Forming a second insulating layer over the first insulating layer and the first wiring layer; PA1 Patterning the via holes in the second insulating layer; PA1 Etching the vias holes in the second insulating layer; PA1 Forming via hole plugs PA1 Forming a second conductive layer over the second insulating layer and the plugged vias; PA1 Patterning the second conductive layer; and PA1 Etching the second conductive layer to form a second wiring layer.
This process includes four steps of fine patterning and etching which are required for the fabrication of conducting paths, i.e., for the formation of the holes, for the structure of the first wiring layer, for the formation of the vias, and for the structure of the second wiring layer. The patterning and etching processing steps are expensive and time consuming resulting in increased cost for the integrated circuit device.
A need has therefore been felt for a process for the fabrication of the interconnections between the semiconductor substrate and the wiring layers of an integrated circuit which would reduce the number of fine patterning and etching steps, thereby reducing the cost of the circuit and the reducing the fabrication time.